Professions of a Silicon Valley Double-E
Saturday, May 23, 2009
  Breaking into Analog IC
Recently a friend who was one of my industry contacts when I was an undergrad (many many years ago between the invention of the PC and the invention of the internet) who is considering getting into analog design asked for some ideas on how to get a job in this arena.

While of course the key, as in any job situation, is to be seen as a reliable, competent engineer with enough experience in the field.
And Analog IC design may not be the future hot spot of design that he was hoping.

To be considered as reliable you probably need to be referred as a Friend of a Friend. Really.

To be seen as competent, it helps if people can see examples of your work. A Paper, A Patent. A successful chip project they've heard of. Your Thesis, a Circuit you designed and Fabricated in school.

Of course since he was at the end of his Ph.D, It was too late to suggest the best course of action (if you REALLY want to do analog design) : Get the MSEE/Ph.D under a well respected analog Prof. - Which of course is one route to building that network. After all you can be the greated Analog designer since Bob Widlar, but if no one else knows this, it won't help your salary.


Here is my answer: In case it helps you think of some ideas for your situation.

1. Write a paper on one of the Analog Circuits you developed as a part of your PhD research. Get that published. Give a talk on that. IE whats tricks did you have to play to get the Speed up to what was needed? to get good Yield?
(ie present at xxxx(local) SSCS chapter?)

2 Read: JSSC aka the Red Rag. pub cycle for that is prob 6 months if you can get in. only ~50% of submissions accepted.
Also Transactions on VLSI.

3. Books: Johns and Martin, Grey [lewis, Hurst] & Meyer. Razavi.

4. Conferences: ISSCC is premier. Other good ones are CICC (visit us here in SJC!)
RFIC. - best ones are the SSCS sponsored conferences.
for modeling and simulation, BMAS (right after CICC )is great, but much smaller.

Tools: With your device/process background, Verilog-A is a sure thing.. its the new "compact model" language. Verilog-AMS is even better. - but modeling is becoming a subskill to verification.
Know how to run analog sims.. and RF analyses too..
most analog designers work in the Cadence Analog Design Environment..
the rest live with spice netlists and run Hspice.. Nanosim, Hsim, etc..


I hope these ideas help.

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Ruminations about the Electrical Engineering profession as practiced in Silicon Valley by an IEEE Senior Member. Disclaimer: All Posts here are official IEEE business in that they are messages about IEEE activities from an IEEE volunteer. These messages do not constitute official records of R6-PACE activities, nor official IEEE or IEEE-USA policy statements. Website: http://www.ieee.org/scv/pace

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When he is not working on IEEE stuff, Jonathan does Mixed Signal Design Verification at Qualcomm. Senior Member IEEE. Founder IEEE-SCV-SSC (the first Solid State Circuits chapter). Past Section Chair, Santa Clara Valley Section - the Largest Section. Co-founder IEEE-SCV-CAS. IEEE-SSCS Membership chair 2001-2003. IEEE SSCS chapters Committee member. IEEE-SCV-PACE committee member 2001- IEEE-SCV-PACE Chair 2006-2007. IEEE R6 PACE coordinator.

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